The field of the invention is that of packaging integrated circuits, in particular circuits processing signals in the gigabit range.
In the field of packaging integrated circuits, it is well known that unmatched impedances will result in reflections at the interface and possible signal degradation. Those skilled in the art are well aware of formulas used to calculate geometrical structures that provide a desired impedance.
The problem addressed by the present invention is that of reducing transmission losses in an ultrawideband (0-30 GHz) frequency range while maintaining constant impedance throughout the length of the line. Many prior art approaches are narrowband and do not satisfy the frequency requirement.
As frequency increases, losses that depend on the conductor width increase. Simply increasing the width would change the impedance of the line.
One prior art approach specific to a microstrip transmission line on the surface of the package (Japanese Patent Abstract 11330808) changes the vertical distance to a ground plane only below the microstrip. Transmission lines on the surface are constrained by space considerations. It remains, however, a problem for the art to provide a structure adapted for signal transmission through the interior of a package with the desired impedance and reasonable cost.
The invention relates to an integrated circuit packaging structure that provides a signal-carrying member passing through the body of the package and having two sections with different appropriate dimensions for low-loss transmission, together with ground planes spaced appropriately to maintain the desired impedance.
A feature of the invention is the increase in vertical spacing both above and below the signal member when the signal member is widened to decrease signal power loss.
Another feature of the invention is the creation of an aperture in the closest ground plane to the signal member, so that the next ground plane in vertical position can act to maintain the desired impedance.